1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device. More particularly, the present invention relates to a method of manufacturing the floating gate of a stacked-gate nonvolatile memory unit such that the floating gate has a better external profile and the memory unit has a higher performance.
2. Description of the Related Art
Stacked-gate nonvolatile memory can be classified roughly into erasable programmable read only memory (EPROM), electrically erasable programmable read only memory (EEPROM) and flash memory. All these memories use an isolated or floating gate as the place for storing electric charges. When the floating gate contains electric charges, a logic state of `1` is assumed. On the other hand, if no electric charges are present, the memory is assumed to be in a logic state of `0` by default. To tore electrons inside the floating gate, the electrons have to pass through a tunneling oxide layer. Therefore, the thickness of the tunneling oxide layer is one of the critical factors in determining how many electrons can pass through. If the tunneling oxide layer is too thick, very few electrons are able to pass through and there will not be enough electrons inside to indicate a logic state of `1`.
FIG. 1 is a schematic cross-sectional view showing the floating gate of a conventional stacked-gate type nonvolatile memory unit. A gate oxide layer 110 and a polysilicon floating gate 120 are formed over a substrate 100. After the floating gate 120 is patterned, a silicon oxide layer 130 is formed over the floating gate 120 by performing a thermal oxidation. An oxide/nitride/oxide (ONO) composite layer (not shown in the figure) is next formed over the silicon oxide layer 130 serving as interpolysilicon dielectrics (IPD).
However, during thermal oxidation, the lower edge portion 140 of the floating gate 120 is likely to be over-oxidized due to oxygen diffusion. Consequently, a thicker layer of oxide is formed having a shape very similar to a bird's beak formation when a field oxide layer is formed on a substrate by oxidation. In addition, the portion of the oxide layer 110 below the floating gate 120 is actually a channel (i.e. the tunneling oxide layer 115) through which hot electrons move in and out of the floating gate 120. As miniaturization of devices continues, the tunneling oxide layer 115 will contain a proportionally greater amount of thick oxide layer 140 so that hot electrons enter and leave the floating gate 120 with greater difficulty. Consequently, writing data into or erasing data from a nonvolatile memory unit becomes more unreliable.